Plasma display panels (hereinafter, referred to as “PDPs”) are one type of thin display device, and include direct current (DC) and alternating current (AC) types. AC PDPs have a high technological potential in view of large screen sizes, and among AC PDPs, surface discharge PDPs have attracted attention in particular due to their lifetime properties.
1. PDP Structure
FIGS. 11A and 11B show a structure of a surface discharge AC PDP that is constituted from a front plate 702 and a back plate 703 disposed in opposition to sandwich a discharge space therebetween.
As shown in FIGS. 11A and 11B, the front plate 702 is constituted from a glass substrate 710 whose main surface on the discharge space side has a display electrode pair 704 constituted from a scan electrode 705 and a sustain electrode 706, a dielectric layer 707, and a protective layer 708 laminated successively thereon. The scan electrode 705 and the sustain electrode 706 are disposed in opposition to sandwich a gap D therebetween of 50 [μm] and 100 [μm], and are each constituted from a bus electrode 709 and transparent electrodes 755 and 756 respectively.
The bus electrodes 709 are metallic and narrow with a film thickness of 5 [μm] to 6 [μm], and are disposed on main surfaces of the transparent electrodes 755 and 756. The bus electrodes 709 are provided by, for example, a thick film process of printing a layer of Ag paste, and baking the printed layer.
The dielectric layer 707 is formed by a thick film process of baking a low melting glass paste that includes a lead glass material as a main component and has been applied by a printing method, and the film thickness of the dielectric layer 707 is set to approximately 40 [μm].
The lead glass material used in the dielectric layer 707 has, for example, a relative dielectric constant ∈ of approximately 13.
The protective layer 708 has a film thickness set to several hundred [nm], and a main component thereof is MgO having good electrical insulating properties.
An area where one display electrode pair 704 and a data electrode 712 included in the back plate 703 three-dimensionally intersect is called a discharge cell, and the areas shown in FIGS. 11A and 11B correspond to discharge cells.
It is the display electrode pair 704 that directly contributes to PDP image display, whereas the data electrode 712 is for selecting a discharge cell, which is a unit of image display, and does not directly contribute to emission in image display.
The PDP is made up of discharge cells, which are units of image display, arranged in a matrix configuration. The PDP is assumed to be a PDP apparatus that includes a known drive circuit, control circuit, and the like.
2. PDP Drive Method
Display of the PDP is driven by an address-display separation drive scheme that includes three operation periods, which are specifically (1) an initialization period in which all display cells are put into an initialized state, (2) a data writing period in which the discharge cells are addressed, and display states corresponding to input data are selected and input to the addressed discharge cells, and (3) a sustained discharge period in which the discharge cells in the display states are caused to perform display emission.
In (3) the sustained discharge period, rectangular voltage pulses of approximately 200 [V] and having mutually different phases are applied to the scan electrode 705 and the sustain electrode 706 in discharge cells in which wall charges corresponding to input data have been formed during (2) the writing period. In other words, applying alternating voltages between display electrode pairs causes the generation of pulse discharges in discharge cells to which display states have been written, each time there is a change in voltage polarity.
Xenon is excited by the sustain discharge, ultraviolet radiation is emitted from the excited xenon, and the ultraviolet radiation is converted to visible light by a phosphor layer 715, thereby causing image display.
However, as previously mentioned, in a conventional PDP the bus electrodes 709 and the dielectric layer 707 are formed by thick film processes that include a baking step. The baking step involves high temperatures between 500 [° C.] and 600 [° C.], and there are cases in which the binder baking material included in the paste remains in the bus electrodes 709 after baking.
Therefore, during baking of the dielectric layer 707, gas bubbles readily form in portions where the bus electrodes 709 and the dielectric layer 707 are in contact, and areas of the dielectric layer 707 corresponding to such bubble formation areas are thinner than other areas of the dielectric layer 707. Also, given that the dielectric layer 707 has a low dielectric breakdown voltage of approximately 2.5×105 [V/cm] since the density of the baking material is low, thin areas are formed in the dielectric layer 707, resulting in a low withstand voltage in the PDP. As such, dielectric breakdown readily occurs in the dielectric layer 707 during high voltage application etc. in the initialization period.
It is therefore necessary to set the film thickness of the dielectric layer 707 to a high 40 [μm] in a conventional PDP in order to improve the withstand voltage of the dielectric layer 707, and as a result, it is necessary to set the discharge inception voltage and discharge sustaining voltage high, which makes it difficult to improve the luminous efficiency.
One technique that has been disclosed in response to this problem (e.g., see patent document 1) is a dielectric layer that has a multilayer film structure formed by using a vacuum deposition method or sputtering method to laminate, in the stated order, a first layer composed of Al2O3, a second layer composed of glass including 80% SiO2, and a third layer composed of Al2O3, where the first layer directly covers electrodes including double layers of Cr and Cu formed by vacuum deposition.
According to the invention recited in patent document 1, cracks do not occur since an Al2O3 film formed by a thin film process using a vapor deposition method or sputtering method is used as the first and third layers, and using glass including 80% SiO2 as the second layer enables the formation of a thin dielectric layer in which cracks do not occur.
Further disclosed (e.g., see patent document 2) is a dielectric layer composed of a bottom layer and a top layer, the bottom layer being composed of a metal oxide formed on an electrode by a vacuum process such as a CVD method, sputtering, or deposition, and the top layer being composed of dielectric glass formed on the bottom layer.
According to the invention recited in patent document 2, a thin dielectric layer in which dielectric breakdown does not readily occur during PDP driving can be formed by, when coating the dielectric layer on an Ag electrode formed by printing an Ag paste and baking the paste, first using a CVD method to form a layer of a metal oxide that generates a hydroxyl group on the surface such as ZnO, ZrO2, MgO, TiO2, SiO2, Al2O3, Cr2O3, etc. with a thickness of 0.1 [μm] to 10 [μm] on a surface of the Ag electrode, and then coating a dielectric layer composed of dielectric glass thereupon.
Also, it is known in such a PDP that a microscopic electrode pair may be disposed in the gap D as a means for reducing the discharge inception voltage and discharge sustaining voltage to lower energy consumption.
For example, patent document 3 discloses a pair of auxiliary electrodes (trigger electrodes) that are disposed in a gap between a scan electrode and a sustain electrode, where each of the auxiliary electrodes is provided with wings at a center of a discharge cell, so as to have a wider area at the center portion of the discharge cell than at the edges thereof. Since discharges occur in gaps between the provided wings, sustain discharges occur reliably even with a low discharge sustaining voltage and discharge inception voltage, thereby enabling an improvement in discharge efficiency during sustain discharges.
Also, patent document 4 discloses, as shown in a discharge cell 800 of FIG. 12, a scan electrode 805 and a sustain electrode 806 constituting a main display electrode pair 802, and an auxiliary discharge electrode pair 801 that is formed on opposing faces of the scan electrode 805 and the sustain electrode 806 to sandwich a gap g therebetween that is narrower than a gap G sandwiched by the electrodes 805 and 806, and has a higher sheet resistivity than the main display electrode pair 802. Furthermore, the applied voltage pulse is a rectangular pulse that has a high luminous efficiency, and the voltage value thereof is set such that a discharge does not occur between the scan electrode 805 and the sustain electrode 806 when there is not discharge between the auxiliary display electrodes constituting the auxiliary display electrode pair 801, but does occur between the scan electrode 805 and the sustain electrode 806 when there is a discharge between the auxiliary display electrodes. Note that FIG. 12 is a relevant planar diagram indicating part of a display electrode pair of a PDP, where the view is from a back plate not depicted, and the area enclosed in a dashed double-dotted line corresponds to the discharge cell.
Employing this structure and setting the voltage value as mentioned above enables control of the discharge delay time and shorter discharge delays, and can be expected to reliably initiate sustain discharges even if the discharge inception voltage is lowered.
Patent document 1: Japanese Patent Application Publication No. S55-143754
Patent document 2: Japanese Patent Application Publication No. 2003-7217
Patent document 3: Japanese Patent Application Publication No. 2001-236895
Patent document 4: Japanese Patent Application Publication No. H04-4542